Generally, known metal-oxide-metal (MOS) transistors have relatively high sheet resistance at the interface between metal interconnects. The high sheet resistance causes high power consumption and delivers a great deal of heat into the integrated circuit formed thereby, which may affect the operational characteristics of the integrated circuit. Accordingly, to reduce the high sheet resistance, a method that forms a silicide layer on source and drain regions and a gate electrode has been developed. In the known method of forming the silicide layer, a metal layer such as Ti that can chemically react with silicon is first deposited on a gate electrode and spacers as well as on source and drain regions. While a thermal treatment for the metal layer is carried out one or two times, the metal layer chemically reacts with polysilicon of the gate or silicon of the source or the drain so that the silicide layer is formed and the remainder of the metal layer that has not reacted with anything is removed by an etching process.
The foregoing method is called a self-aligned silicide (hereinafter referred to as “salicide”) process because a silicide layer is formed without any mask process defining where the silicide layer will be formed. The salicide layer formed using the forgoing method greatly affects the standby current characteristics of a semiconductor device as well as characteristics of its leakage current, which vary based on deposition thickness. Therefore, it is important to analyze the characteristics of the junction leakage current due to the salicide process.
FIGS. 1a through 2c are views illustrating examples of known test patterns for measuring the junction leakage current due to the salicide layer. FIG. 1a is a top view illustrating a test pattern of area type, and FIG. 1b and FIG. 1c are cross-sectional views illustrating test patterns taken along the line A-A′ and the line B-B′, respectively.
FIG. 2a is a top view illustrating a test pattern of peripheral type, and FIG. 2b and FIG. 2c are cross-sectional views illustrating test patterns taken along the line A-A′ and the line B-B′, respectively. Both test patterns of area type and peripheral type are identical except that they are distinguished by the number of shallow trench isolation (hereinafter referred to as “STI”) structures or device isolation structures formed along the line B-B′.
The processes for forming the salicide pattern described above are now described. Referring to FIG. 1b, an STI 2 for device isolation is defined in a silicon substrate 1 of a predetermined impurity type. A well region (not shown) is formed by implanting impurities identical to the substrate type. An active region 3 including source and drain regions is formed by implanting impurities opposite to the type of impurities implanted in the well. A salicide layer 4 is formed on the entire surface of the active region 3 and an interlayer dielectric layer 5 is deposited on the entire surface of the substrate. After a photoresist pattern (not shown) is formed to expose the region where via holes will be formed, the interlayer dielectric layer 5 is dry-etched by using the photoresist pattern as a mask, so that via holes 6 are completed and the salicide layer 4 is exposed. Next, the via holes 6 are filled with a predetermined conductive metal and planarized. Metal interconnects 7 are formed on the interlayer dielectric layer including the via holes so that a test pattern is completed.
However, if the junction leakage current is measured by the test pattern, the junction leakage current from the salicide layer itself is difficult to measure because the salicide layer exists through the whole active region and comes in contact with the edge (the dotted region in FIG. 2c) of the STI, which is greatly affected by a leakage current.